Integrated circuit (IC) design, especially highly integrated system-on-chip (SOC) devices, involve a number of non-trivial issues, and transistor structures have faced particular complications, such as those with respect to achieving devices with low-power dissipation side-by-side with high performance devices. Finned transistor configurations include a transistor built around a thin strip of semiconductor materials (generally referred to as the fin). The transistor includes the standard field effect transistor (FET) nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device effectively resides on the outer sides of the fin, beneath the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides substantially perpendicular to the substrate surface) as well as along the top of the fin (side substantially parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such configurations have been termed as finFET and tri-gate transistors. Other types of finned configurations can also be used, such as so-called double-gate finFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin, for example).